Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
| Date             : Wed May  6 07:48:52 2026
| Host             : XPS13Plus running 64-bit major release  (build 9200)
| Command          : report_power -file power_active.txt
| Design           : top
| Device           : xc7a35tcpg236-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------------------------------------------------------------------------------------+
| Total On-Chip Power (W)  | 0.114                                                                                      |
| Design Power Budget (W)  | Unspecified*                                                                               |
| Power Budget Margin (W)  | NA                                                                                         |
| Dynamic (W)              | 0.042                                                                                      |
| Device Static (W)        | 0.072                                                                                      |
| Effective TJA (C/W)      | 5.0                                                                                        |
| Max Ambient (C)          | 84.4                                                                                       |
| Junction Temperature (C) | 25.6                                                                                       |
| Confidence Level         | Medium                                                                                     |
| Setting File             | ---                                                                                        |
| Simulation Activity File | C:/Users/taega/Documents/OpticalFlowAccel/RTL_accel.sim/sim_1/behav/xsim/power_active.saif |
| Design Nets Matched      | 23%   (350/1510)                                                                           |
+--------------------------+--------------------------------------------------------------------------------------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     0.003 |        3 |       --- |             --- |
| Slice Logic              |     0.005 |     1258 |       --- |             --- |
|   LUT as Logic           |     0.003 |      308 |     20800 |            1.48 |
|   LUT as Distributed RAM |     0.001 |      192 |      9600 |            2.00 |
|   Register               |    <0.001 |      468 |     41600 |            1.13 |
|   LUT as Shift Register  |    <0.001 |       32 |      9600 |            0.33 |
|   CARRY4                 |    <0.001 |       47 |      8150 |            0.58 |
|   F7/F8 Muxes            |    <0.001 |      102 |     32600 |            0.31 |
|   Others                 |     0.000 |       13 |       --- |             --- |
| Signals                  |     0.007 |      985 |       --- |             --- |
| Block RAM                |     0.002 |      0.5 |        50 |            1.00 |
| DSPs                     |     0.001 |        1 |        90 |            1.11 |
| I/O                      |     0.024 |       19 |       106 |           17.92 |
| Static Power             |     0.072 |          |           |                 |
| Total                    |     0.114 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint    |       1.000 |     0.027 |       0.017 |      0.010 |       NA    | Unspecified | NA         |
| Vccaux    |       1.800 |     0.014 |       0.001 |      0.013 |       NA    | Unspecified | NA         |
| Vcco33    |       3.300 |     0.008 |       0.007 |      0.001 |       NA    | Unspecified | NA         |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccbram   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                               | Action                                                                                                     |
+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                      |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                |                                                                                                            |
| I/O nodes activity          | Medium     | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes        | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                          |                                                                                                            |
|                             |            |                                                       |                                                                                                            |
| Overall confidence level    | Medium     |                                                       |                                                                                                            |
+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 5.0                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 4.6                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+---------+--------+-----------------+
| Clock   | Domain | Constraint (ns) |
+---------+--------+-----------------+
| sys_clk | clk    |            10.0 |
+---------+--------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+------------+-----------+
| Name       | Power (W) |
+------------+-----------+
| top        |     0.042 |
|   u_accel  |     0.017 |
|     h_sxx  |     0.003 |
|     lb_sxx |     0.009 |
|     v_sxx  |     0.003 |
+------------+-----------+